PollEx Update List
Period : 2010.10.15~2010.11.17
|| [ExtractPDBB - ODB++]
Changed ODB++ I/F Option
- ExtractPDBB40_l /O "DesignDir" "PDBBSaveDir" "PDBBSaveFileName" /S:Option /U:Unit
Option Dialog Display
- If user wants to select the data type(PCB/STRIP/PANEL), do not list "/S:Option" script.
[Net 2D/3D Viewer]
Added : Reference Name display.
[Draw - Void Turret]
Zuken PWS : To consider turret width for Void area.
|| [Interface - Cadence Concept]
Added : Cadence Concept Interface.
① Select the installed library(CDS).
- If library existed on local PC, it's not necessary to define CDS.
② Select the installed Concept library(CHDL).
- If library existed on local PC, it's not necessary to define CHDL.
③ Select the project directory to import.
WorkLib folder, cds.lib, xxx.cpm must be located in Project Directory.
[ExtractSDBB - Cadence Concept 추가]
Added : Cadence Concept Interface Command.
- ExtractSDBB40_l /C "SDBBSaveDir" "SDBBFileName" "ConceptProjectDir" /CDS:"CDSLibraryDir" /CHDL:"CHDLLibraryDir"
[ExtractSDBB - EDIF2.0 Interface Option 추가]
Added : EDIF2.0 Interface Option
- ExtractSDBB /E "SdbbSaveDir" "SdbbFileName" "EDF File Name" /PND:PartNameDeclarationDefine /RND:PartNameDeclarationDefine
- /PND : Part Name Declarartion
- /RND : Reference Name Declarartion
- /RFC : Remove first net name charactor
|| [Component - U Name Overlap]
New Item : To check the overlap Reference Name and Hole, Silk, Component.
① Reference Name to Hole: Checking overlap U name and hole.
② Reference Name to Silk: Checking overlap U name and silk.
③ Reference Name to Component: Checking overlap U name and component.
[Component - 1st Pin Mark]
Added option : To check the 1st Pin Mark as designed board figure. It checks the mark existence with given area value.
[Component - Polarity Mark]
Added option : To check the Polarity Mark as designed board figure. It checks the mark existence with given area value.
[Pad - Hole Through Pad]
Added option : Can except the certain Via size.
[Board - PCB Outline Sharp Angle]
Added option : Can check the Board Outline that it's designed as Arc or not.
[FPCB - Silk Cover In Via]
Added option : Can check the silkscreen existence on Via of Top/Bottom layers.
[Board - PCB Mark]
Added option : Can give a tolerance from PCB Mark to other components.
[Board - Fiducial Mark]
Added option : Can check the symmetry placement of Fiducial Mark.
[Pattern - Unrouted Net]
Added option : Can detect mismatched point between start point and end point of Net.
[Component - Reverse Placement Spacing]
Added option : Can check the distance between DIP type component's Solder Mask and pad of reverse side.
[Drill Size - Hole Distance]
Added option : Can select the type of Hole among Via Hole, Dip Pad Hole, and Figure Hole to verify.
|| [DFE Server Service Command]
Added : DFE Command Option.
- PollExPCB_l /DFEC "PDBB " "DFESI" "DFER" "DFEE" /R:"excel file path" /L:"Log file path" /BX:"Base Excel File Path" /PNCLS:"PNCLS file path" /CDB:"Comp DB Path" /NDB:"Net DB Path"
- /PNCLS : PNCLS file path
- /CDB : Component DB path
- /NDB : Net DB path
PollEx Update, 17th November 2010
Please get download new version and do upgrade for your convenience.
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