PollEx PCB Signal Integrity

PollEx SI (Signal Integrity) is a fast, accurate, and easy-to-use signal integrity validation program for analyzing PCB designs. It allows users to detect and correct signal integrity problems during design stage so that costly design iterations are eliminated or significantly reduced.

[Running structure of PollEx SI]


  • - Signal integrity validation capabilities are tightly integrated into PollEx PCB which is interfaced with various PCB design tools.
    - Complete signal integrity solutions are provided throughout the PCB design stages including the pre-design and post-layout stages.
    - Time-domain analysis capabilities include wave propagation delay, reflection, crosstalk, and eye diagram analyses.
    - Frequency-domain analysis capabilities include the calculation of scattering, admittance and impedance parameter matrices.
    - Fully automated built-in analysis features include layer stack-up optimization, net topology analysis and post-route signal integrity validation.
    - Both transistor level SPICE models and behavioral SPICE and IBIS models can be used for the driver/receiver/terminator device models.
    - Various IC package pin parasitic models such as lumped RLC, distributed RLC, SPICE netlist, and S-parameters can be used for the signal integrity analysis.
    - Built-in Polliwog SPICE is employed for accurate simulation.
    - Built-in electromagnetic integral equation solver using method of moments calculates accurate frequency-dependent RLCG matrices for coupled lossy dispersive transmission lines and generates equivalent broad-band SPICE netlists using network synthesis methods.
    - Built-in 3-D electro-dynamic finite element solver extracts S-parameters of coupled vias and generates equivalent broad-band SPICE netlists using network synthesis methods.
    - Built-in part and material editors allow user to easily generate I/O buffer models, package parasitic models, and material data and construct part and material libraries for repetitive uses.
    - Composite nets are automatically identified, and the connecting passives can be modeled as RLC, SPICE netlist, and S-parameters for the composite net analysis.
    - Differential net pairs are automatically identified, and analyses are performed for the differential pairs.
    - Can generate input data files for third-party EM solvers and power integrity analysis tools.
    - PollEx SI modules have been designed for common use by multiple engineering disciplines so that design project members can quickly validate the designs and design changes throughout the design process.

Major Benefits

  • - No need for interfaces or data transfer between the PCB design and signal integrity analysis tools.
    - No need for purchasing and maintaining expensive stand-alone signal integrity tools.
    - Signal integrity experts can oversee much more designs since most built-in signal integrity validation features can be effectively used by electrical engineers, PCB designers, and manufacturing engineers.
    - Close collaboration among design project members allows better designs in reduced design time.