PollEx PCB DFM

PollEx DFM is rule-based PCB verification software for manufacturing engineers. Using PollEx PCB as its basis PollEx DFM supports PCB design data in various ECAD formats. It allows users to detect design errors which result in costly manufacturing defects.

Reduces Time and Cost of Design to Manufacturing Process

Its features allow users to reduce expense and loss of time occurring in a mass production cycle. Numerous manufacturing defect items are checked against the PCB design data, and any design errors are reported at the point of error so that they are easily identified and corrected. Consequently employing PollEx DFM results in significant reduction of manufacturing defects.

[Running structure of PollEx DFM]

Features

  • - User-optimized environment for setting multiple rules.
    - Contains all intelligent information from ECAD database with the use of PollEx PCB.
    - Verification of assembly and fabrication against conceptual and physical designs.
    - Provides customized functions of reflecting requirements of field engineers.
    - Can manage checking history as report with screenshots of real error points.
    - Efficient use of Running Core and Pre/Post Processors.


Major checking items

Over 120 Items

  • Spacing optimization for components

    Component Spacing, Reverse Placement Spacing, Clinch Spacing, Min Pad Spacing in Component

    Mark existence for manufacturing equipments

    First Pin Mark, IC Visual Mark, Center Mark, Polarity Mark, Pin Count Mark, Fiducial Mark, PCB Mark, SMT Direction Mark

    Adequate condition for manufacturing environment

    Prefix Check, Pair Component, Silk to Silk, Reference Name Silk, Reference Name Ordering, Pin Arrangement, Silk Print Between Two Pins, Variant Pad Shape, Edge Pin Size, OSP, Nearest Comp Silk, Specific Area, Pad Size by Pin Pitch

    Annular ring optimization

    Dip Annular Ring, Via Annular Ring

    Placement optimization

    Component Count, Component On Component, Component Placement, Prohibited Component, Placement At Reverse Side, Standard Component

    Tooling

    Screw, Pin Mark Match Check, Hole Mark Match Check, Pad Match Check, Board Outline Match Check

    Drill condition

    Drill Size of Hole, Drill Size of Pin, Drill Size of Via, Under Hole/Via, Hole Distance, Gas Hole, Drill Scan, Similar Hole Size

    Pin pad condition

    Hole Through Pad, Silk On Pad, Dummy Pad, Via Spacing, Teardrop, Via S/R Spacing, SR Pad, Remove Copper, Thermal Pad, Copper Connected Pad, Minimum Via Land Size, Via Over Stack

    Condition of PCB space

    Board Spacing, PCB Outline Spacing, Guide Hole, Guide Line, Cutting Region, PCB Outline Sharp Angle, Array Board Size Check, Label Box, Missing Hole, Min Silk Width, Jig Hole, Routing Slit, SM Violate, Dummy PCB, Board Origin Offset, V-Cut, Sub Board MisArrangement, Data Existence, Ground Wall

    Net verification

    Connected Pad, Lines Between Two Pins, Net to Net, Min Width, Pad to Net, 1 Pin Nets, Crack Pattern, Object to Object, Unrouted Net, Keep Out Pattern

    FPCB

    Bending Area, Stiffener, Round Pattern, Bonding Pad, Silver Paste, Min Via Spacing, Manufacturing Process, Coverlay, Bonding Area

    Condition for specific product

    LED, Text Existence, Key Pad, Dome Sheet Guide Hole, TCP Bonding Mark, TCP Dummy Pad, TCP Pad, TCP Align Hole, FPC Dummy Pad

    BGA component

    Spacing from Other Object, Underfill